This paper reports on a statistical study of the ferroelectric and capacitive memory characteristics of 7-nm thick HfxZr1-xO2 capacitors (FeCAPs) fabricated on 300 mm wafers, comparing standalone devices against integrated ones into the BEOL of a 22 nm FDSOI CMOS technology. Although remanent polarization values differ between standalone (25.7 µC/cm2) and integrated devices (8.5 µC/cm2), the Capacitive Memory Window at 0 V (CMW@0V) remains in the same range. Integrated devices, comprising 4092 FeCAPs connected in parallel, exhibit a CMW@0V of 0.083 µF/cm2 (compared to 0.12 µF/cm2 for 100 µm wide standalone) and a low wafer-level variation coefficient of 6.9%. Observations on spatial correlations between device performance and wafer position suggest that process-related material inhomogeneities may be responsible. Finally, we explore the analog synaptic capability of integrated FeCAPs through a multilevel programming scheme achieving up to 30 capacitance states.
