As hardware security becomes a major requirement in edge-AI systems, countering Side-Channel Attacks (SCAs) with minimal overhead is increasingly important. In recent CMOS technologies, digital Advanced Encryption Standard (AES) cores require a step-down converter from the system bus voltage. Such a converter can therefore also be exploited as an intrinsic first layer of side-channel protection. To guide the design of future AES-based systems, three fully integrated SCC topologies are experimentally compared in a 22nm FD-SOI to supply and protect an AES core. At system level, AES power consumption is reduced by up to 50% thanks to 3:1 voltage scaling, leading to a negative power overhead compared to the 2:1 baseline. In addition, the number of traces required to recover the key is improved by up to 114× and 750× for CPA and TVLA, respectively, compared to an unprotected AES. These results show that SCC topology can simultaneously reduce system power and provide an intrinsic first line of defense against side-channel attacks.
