A Study on MRAM Across Memory Hierarchies for Edge KWS Adaptive Power Cycling
Student Contest:
No
Affiliation Type:
Research Facility
Keywords:
Speech processing, Data Movement, low-power SoC, MRAM, Power Management, Memory Hierarchy, Duty Cycling, Energy Efficiency, edge AI, Deep Learning
Abstract:
To process Keyword Spotting (KWS) at the edge, achieving high energy efficiency is crucial for long-term operation in battery-powered devices. Since speech occurs intermittently, adaptive power cycling can be used to conserve energy by powering the circuit off during inactive periods. This study investigates the impact of using on-chip Magnetoresistive Random Access Memory (MRAM) as a) non-volatile memory (NVM) for booting and b) as read-only memory for NN parameters, directly serving a MAC engine. Using a set of Recurrent Neural Networks (RNNs), our results demonstrate that MRAM reduces the booting energy consumption for parameter loading by 345x compared to off-chip Flash. Overall, on-chip MRAM-based operation enhances energy efficiency by up to 5x compared to always-on processing and by 280x compared to power cycling with off-chip Flash. Employing on-chip MRAM for NN weight storage improves energy efficiency by 20% over SRAM-based memory for a 60 kB RNN, while larger RNNs benefit more from scratchpadonly computation. These findings highlight the potential of on-chip MRAM in enhancing energy efficiency for edge speech processing.
