CIMS: A CAM-Based In-Memory Sorting Architecture for Efficient Top-K Ranking
Student Contest:
No
Affiliation Type:
Academia
Keywords:
In-memory sorting, content-addressable memory, data analytics, processing-in-memory
Abstract:
This paper presents a novel Content-Addressable Memory (CAM)-based in-memory sorting architecture. By enhancing sorting parallelism and narrowing search scope, our design optimizes ranking energy efficiency and throughput while minimizing data movement. A Parallel Sorting Unit (PSU) is introduced in the CAM, utilizing transistors with high, standard, and low threshold voltages, with carefully configured sizes to control Match Line (ML) discharge rates, reflecting the numerical magnitude of stored data. The proposed two-stage sorting strategy combines comparison-free in-memory sorting with Compare-And-Swap (CAS) unit-based sorting to narrow the search range and skip redundant operations. Simulated in a 22 nm CMOS process, CIMS achieves a throughput of 157M to 631M numbers per second for databases of 1k and 1M scales. Compared to the stae-of-the-art work, our design delivers a 1.3x to 1.7x improvement in throughput and a 1.8x to 9.4x enhancement in energy efficiency, paving the way for future research into scalable in-memory sorting systems.
Track ID:
15.12
Track Name:
Integrated Circuits and Systems for Intelligent Edge and Biomedical Applications
