Multi-Gate Technology and SJ Devices Session
Session Type: Lecture
Session Code: HV-2
Location: Lecture Room
Date & Time: Thursday June 05, 2025 (08:40 - 10:20)
Chair: Ayanori Gatto,
Craig Fisher

 

    Papers are listed in the order they will be presented.

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My Sched		Paper
Id		TopicTitle/Author
5339 1 A New Dimension of Hybrid Switches: Dual-Gate IGBT and SiC MOSFET with Coordinated Gate Control
Roman Baburske, Alexander Philippou
5116 1 Negative Gate Capacitance-Free Split-Gate-Resistance-Separation CSTBT™ for Ultra-Low Switching Loss
Kazuya Konishi, Koyo Matsuzaki, Kohei Onda, Kohei Sako, Shinya Soneda
5223 1 Carrier-Extraction Mechanism for MOS-Controllable Stored-Carrier Diode (MOSD)
Hiroshi Suzuki, Yujiro Takeuchi, Yusuke Takada, Takashi Hirao, Tsubasa Moritsuka, Masaki Shiraishi, Tetsuo Oda, Tomoy...
5021 1 Next-Generation Superjunction Power Device with Trench Sidewall Doping
Chia Liang Liao, Lucio Renna, Voon Cheng Ngwan, Clelia Galati, Natalia Spinella, Giuseppe Longo, Francesco Patane, Gi...
5004 1 Switching Loss Reduction in Superjunction IGBTs via Analysis of Vertical Charge Imbalance
Tomohiro Tamaki, Atsufumi Inoue, Shiro Hino, Kazuyasu Nishikawa, Makoto Hashimoto, Mitsuhisa Kawase, Yohei Sudo, Tsut...