A 4541 TOPS/W Saliency-Aware Analog Computing In-Memory Macro with Charge-Domain Saliency Detector
Student Contest:
Yes
Affiliation Type:
Academia
Keywords:
Computing In-Memory, Saliency, SAR ADC
Abstract:
This paper introduces the first silicon Saliency-Aware Analog Computing In-Memory (SACIM) macro that dynamically optimizes computational precision based on data importance. Unlike sparsity-based methods that dynamically adjust ADC resolution but conflict with bit-parallel computing, SACIM employs an online charge-domain saliency detector to efficiently identify and prioritize critical operations while preserving full bit-parallel compatibility. It features a novel Super-Skip mode that reduces ADC power consumption by over 70%, and includes a current-integration based multi-bit input driver that provides accurate signal generation at low implementation cost. Overall, these techniques yield a 5.8× energy-efficiency gain over existing sparsity-based approaches. Fabricated in 65nm CMOS, the SACIM prototype demonstrates a peak energy efficiency of 4541 TOPS/W, maintaining high inference accuracies of 92.0% and 69.0% on CIFAR-10 and CIFAR-100 respectively, with minimal accuracy degradation (0.7% and 0.3%) versus full-precision computation. This work highlights the potential of saliency-driven design for achieving energy-efficient, high-performance ACIM-based deep learning accelerators.
